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L6327 L6332
6 / 4 CHANNEL VOLTAGE SENSE GMR PREAMPLIFIER
PRODUCT PREVIEW
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Power Supplies +5Vdc, -5Vdc Current bias or voltage bias (selectable) / Differential Voltage Sense architecture 6 or 4 channel versions 38-pin TSSOP package (for either 6 or 4 channels) Internal reference Resistor for read and write currents Read channel -3dB bandwidth > 400MHz (Rmr=50 ohm no interconnect) Input equivalent preamplifier voltage noise 0.5nV/rtHz nominal Input equivalent MR bias current noise 10 pA/ rtHz nominal MR bias current programmable (5 bit DAC) 1.57.0mA nominal MR bias voltage programmable (5 bit DAC) 65-335mV nominal Programmable gain (100V/V, 150, 200 and 250V/V) and read bandwidth Write frequency up to 300 MHz (Lh=70nH, Rh=20 ohms, Ch=2pF, VEE=-5V) Rise/Fall time 0.6ns ( Iw =40mA 0-pk, Lh=70nH, Rh=20 ohms, Ch=2pF, VEE=-5V) Write current programmable (5 bit DAC) 15-60mA PECL write data input Bi-directional 16-bit TTL Serial interface for head selection, read/write currents selection, chip parameters modification, chip enable, vendor code and fault status read back registers 2-pin mode selection (R/W, MRR) Bank write feature for servo write Digital buffered head voltage DBHV / Analog buffered head voltage ABHV pin (gain 5) Thermal asperity detection & correction with adjustable sensitivity level (6 bit DAC) Automatic successive approximation digital measurement of temperature and Rmr (7 bits) Read and write head open/short detection, low low supply detect and temperature monitoring (high temperature warning and Analog Temperature Diode Voltage measurement) Low write frequency detection. WRITE to READ fast recovery 150ns (same
TSSOP38 ORDERING NUMBERS: L6327 L6332
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head, including 100ns blanking period) Head-to-head switch in READ mode - 10s (nom) Head and MR bias current switching transient current head protection READ-to-WRITE switching 50ns (same head) Programmable read bias during write and bank write operation ESD diode for GMR head protection
DESCRIPTION L6327/L6332 is a BICMOS monolithic integrated circuit GMR differential preamplifier designed for use with four-terminal magneto-resistive GMR read/inductive write heads. It is available as either a six (L6327) or four (L6332) channel device. The devices consist of a voltage-sense, current-bias or voltagebias (selectable), differential input and differential output, low-noise, high bandwidth read amplifier and include fast current switching write drivers which support data rates in excess of 550 Mb/s with 70nH write heads. The GMR preamplifier provides programmable read current / voltage bias and write current (5 bit DAC for the read bias, 5 bit DAC for the write current), fault detection circuitry and servo writing features. Read amplifier gain, write current wave shape (overshoot, undershoot and damping) can be adjusted and a thermal asperity detection and correction circuit can be enabled and programmed with different thresholds (6 bit DAC) through a 16-bit bi-directional serial interface (SDEN, SDATA, SCLK). The device operates from a +5V supply and a -5V supply (nominal). No external components are required as a trimmed or untrimmed resistor for reference current setting is employed.
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February 2001
This is preliminary information on a new product now in development. Details are subject to change without notice.
L6327 - L6332
BLOCK DIAGRAM
VCC (+5V)
VGND (0V)
VEE (-5V)
HW0P WDP
PREDRIVER
HW0N
WDN
FAULT PROCESSOR
Low supply detection, Open/short heads, TA detection, low write frequency, high temperature
3v
WRITE DRIVERS
FLT
HW1/5P HW1/5N WRITE DAC
Imr, Iwr current/voltage low bias RW enable head select
Rdamp Overshoot, Undershhot
3v
SDATA SCLK SEN
SERIAL INTERFACE CONTROL
3v
R/W
HEAD SELECTION & MODE CONTROL
A2D RMR, temp ABHV, MR meas Temperature monitoring TA detection, TA correction
READ DAC
MRR ABHV/ ADTV RDP RDN
Gain boost, Low pass filter High pass filter
HR0P
MR READ INPUT STAGES
HR0N HR1/5P HR1/5N
VREF
L6327/L6332 6/4 CH
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L6327 - L6332
mm DIM. MIN. A A1 A2 b c D E e E1 L k 4.30 0.50 0.05 0.85 0.17 0.09 9.60 9.70 6.40 0.50 4.40 0.60 4.50 0.70 0.169 0.020 0.90 TYP. MAX. 1.10 0.15 0.95 0.27 0.20 9.80 0.002 0.033 0.007 0.0035 0.378 MIN.
inch TYP. MAX. 0.043 0.006 0.035 0.037 0.011 0.008 0.382 0.252 0.020 0.173 0.024 0.177 0.028 0.386
OUTLINE AND MECHANICAL DATA
TSSOP38
Thin Shrink Small Outline Package
0 (min.) 8 (max.)
E1
A2 b
0.010 mm 0.004 inch SEATING PLANE
A
c
e
A1
D Gage Plane 0.25mm 38 20 E Pin 1 identification 19 A1 SEATING PLANE
TSSO3 8M
k L
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L6327 - L6332
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (R) 2001 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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